Parallel mode on-screen display system

ABSTRACT

An on-screen display generator includes a character buffer containing a plurality of entries, and an attribute buffer also containing a plurality of entries. Each entry in the character buffer has a corresponding entry in the attribute buffer. The entries in the character buffer each specify a display character, and the corresponding entry in the attribute buffer specifies the display attributes of the display character. Control circuitry retrieves corresponding entries from the character and attribute buffers substantially simultaneously, and generates a signal representing the image of the display character specified in the retrieved display character entry having the attributes specified in the retrieved attribute entry.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to on-screen display systems fortelevision display systems.

2. Description of the Prior Art

Current television display systems require some sort of textualon-screen display (OSD) system, for displaying means and closedcaptioning, for example. High-end television display systems sometimesemploy advanced bit-mapped graphic displays for display purposes.However, most television display systems still rely oncharacter-per-cell based graphic displays. Because of cost constraints,most such OSD display systems use a single read/write memory (RAM)buffer. Each RAM buffer is large enough to hold one row of textcharacters to be displayed across the screen. Codes representingcharacters to be displayed are stored in the RAM buffer. For example, aprocessor resident within the television system may store charactercodes in the RAM buffer representing a menu for interaction with theviewer; or closed captioning circuitry may extract closed captioninginformation from the received television signal and store charactercodes in the RAM buffer representing that closed captioning informationfor display with the received television image.

An OSD generator counts video lines in the current field of the receivedtelevision video signal, and then operates to display the characterscontained in the RAM buffer when the video lines on which thosecharacters are to be displayed are being scanned. At that point, the OSDgenerator retrieves the character codes from the RAM buffer andgenerates a signal representing the image of those characters. Thepicture elements (pixels) making up the OSD characters are looked up ina character read-only memory (ROM) by using the character code read fromthe RAM buffer, and the video line and pixel locations currently beingscanned, to address the character ROM. The circuitry to retrievecharacter codes from the RAM buffer and to generate the OSD imagerepresentative signal is normally synchronized to the receivedtelevision signal in some manner. The image representative signal thusgenerated may replace or overlay the received television image. The formof OSD generator described above is termed a serial mode OSD generator.In an alternative embodiment of a serial mode OSD, two RAM buffers areoperated as pingpong buffers. One RAM buffer is updated as describedabove while the OSD generator retrieves data from the other.

In known serial mode OSD generator systems, the RAM buffer normallyconsists of one byte (i.e. eight bits) per character, allowing for 256possible characters. However, because the displayed characters arerequired to be displayed in different colors, and with underlining,italics, etc. (termed attributes) for closed captioning and/or menuingsystems, fewer than 256 characters are possible. Each byte in the RAMbuffer may contain either display character data or attribute data. Themost significant bit (MSB) is used to define whether the remaining sevenleast significant bits are a display character or attributes (colorchanges). If the MSB is, for example, a logic ‘1’, the data in this bytespecifies a display character. Consequently, it is possible to specifyup to 127 display characters.

If the MSB is a logic ‘1’, the data in this byte specifies attributes.An attribute byte specifies either a foreground or background color oranother display attribute such as underlining, flashing, italics, etc.Foreground and background colors may either be specified by includingrespective values of red, green and blue (RGB) color components for thespecified color in the attribute byte, or by including an index into apalette table, or possibly into one palette table for foreground colorsand another for background colors. The palette table contains entrieseach specifying a color by including values of respective RGB colorcomponent values. When an attribute change occurs (i.e. an attributetype is retrieved from the RAM buffer), a blank space (usually in thecurrent background color) is generated on the display.

A serial mode OSD generator system provides compact memory usage.However, it is impossible to simply change a character's attributes(foreground/background color, etc.) for all the characters in a line oftext. In addition, because a blank space is displayed when an attributechange is required, the design of the user interface is greatlyinhibited.

One potential way around this problem is to represent every OSDcharacter by 2 sequential bytes in the RAM buffer with a first bytespecifying the display character and a second byte specifying thatcharacter's attributes. In such a system, when OSD information iswritten into the RAM buffer, both the display character and it'sattributes are written into the memory sequentially. That is, theprocessor or closed caption circuitry must write two bytes into the RAMbuffer for each character to be displayed. The OSD generator, in turn,sequentially retrieves the display character byte and then it'scorresponding attribute byte, and generates a signal representing theimage of the display character having those attributes. While feasible,this is not ideal from a software standpoint. The software storing theOSD information must continually write both the display character byteand the attribute byte. However, attributes don't change very often, sowriting attribute bytes for each display character representsunnecessary processing which must be performed by this software.

Another approach to the problem of generation of characters and theircorresponding attributes is described by Edgard, et al. in EP-A-0 395916 entitled SEPARATE FONT AND ATTRIBUTE DISPLAY SYSTEM which waspublished Nov. 7, 1990. Edgard, et al. describe a computer system usingseparate font and attribute buffers. This system, however, is relativelycomplex and employs different processing depending on whetherapplication programs or sub-routines provided by the computermanufacturer are being executed. For example, during subroutineexecution, information stored in registers is written to the attributebuffers when mask information is written to the font buffer. Duringapplication program execution, the attribute value is written to aforeground attribute buffer and zero is written to a background bufferwhile an OR'ed value of the attribute value is written to the fontbuffer. In subroutine read operations, the value in the font buffer maybe obtained or a CRC value may be generated on the entire charactercell. The CRC value can be compared with similar CRC values developed onthe character mask of interest to determine if a character is present inthe cell. During execution of read operations in application programs,the value in the foreground or background buffer is selected based onthe value in the font buffer.

A further example of use of separate attribute and character memories isdescribed by Borg, et al. in U.S. Pat. No. 4,626,479 entitled TERMINALWITH MEMORY WRITE PROTECTION which issued Dec. 9, 1986. In this system,attribute information stored in a RAM separate from character data isutilized for write protection in micro-processor controlled videodisplay terminal. Specifically, unused attribute bits stored in theattribute memory are used to represent a protected field in a characterRAM for a given location or address on the video display and are readfrom the attribute RAM by the microprocessor for restricting access tothe character RAM thus providing write protection for selected portionsof the video display.

Another example of attribute processing is described by Luck, et al., inEP-A-0 149 780 entitled ATTRIBUTE HIERARCHY SYSTEM which was publishedJul. 31, 1985. The Luck et al. system includes a plurality of stacks forstoring data and attributes wherein only the top of the stack is loadedand utilized. The system includes an attribute memory and a characterdata storage, a character data counter and a position register. Anattribute mask and attribute processor control loading of theattributes. A command register pushes, pops or loads to the stacks alongwith a sequence controller input from the attribute processor. A commanddecoder determines sequence of operations for loading attributes andcharacters into row buffers. A stack control flags when a valid load hasoccurred, and if no load occurred, the stack defaults and copy operationoccurs.

It is herein recognized that a need exists for processing character andattribute information in a simplified manner while facilitating moresophisticated on-screen displays as described later. The presentinvention is directed to meeting those needs.

The principles of the invention have application to OSD systems of atype comprising a character buffer (22) containing a plurality ofentries, each entry specifying one of a predetermined plurality ofdisplay characters; an attribute buffer (24) containing a plurality ofentries respectively corresponding to the plurality of entries in thedisplay character buffer, each entry specifying an attribute of thecorresponding display character; and control circuitry (30,50) forsubstantially simultaneously retrieving corresponding entries from thecharacter and attribute buffers and generating a signal representing theimage of the display character specified in the retrieved displaycharacter entry having the attribute specified in the retrievedattribute entry.

SUMMARY OF THE INVENTION

The present invention is characterized in that each entry in theattribute buffer (24) contains data specifying one of a plurality ofentries in a palette memory (40); and said control circuitry (30,50)comprises: a character read-only memory (ROM) (30), coupled to thecharacter buffer (22), and containing a plurality of arrays of pixels,each pixel being one of a foreground pixel or a background pixel,respectively corresponding to the predetermined plurality of displaycharacters, for producing a signal representing a pixel in the pixelarray corresponding to the display character specified by the retrieveddisplay character entry; the palette memory (40) is coupled to theattribute buffer (24) and containing a plurality of entries specifyingrespective image characteristics for foreground pixels and backgroundpixels, for producing respective signals representing the imagecharacteristics of foreground and background pixels in the palette entryspecified by the retrieved attribute entry; and a multiplexer (50),having first and second data input terminals responsive to theforeground and background pixel image representative signals from thepalette memory (40), and having a control input responsive to the pixelrepresentative signal from the character ROM (22), for producing the OSDimage representative signal.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawing:

FIG. 1 is a block diagram of an on-screen display system according toprinciples of the present invention;

FIG. 2 is a memory layout diagram of a display character within thecharacter ROM in FIG. 1; and

FIGS. 3 and 4 are block diagrams of alternate embodiments of anon-screen display system according to principles of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is a block diagram of an on-screen display system in a televisionreceiver according to principles of the present invention. In FIG. 1only those elements and interconnections necessary to understand theinvention are illustrated. One skilled in the art will understand whatother elements are necessary, and will understand how to design,implement, and interconnect those other elements with those illustratedin FIG. 1.

In FIG. 1 a processor 10 has an output terminal coupled to respectivedata input terminals of a buffer RAM 20 and a palette memory 40. In theillustrated embodiment, the buffer RAM 20 is partitioned into acharacter buffer 22 containing data representing display characters forthe OSD, and an attribute buffer 24 containing data representingattributes for the display characters. In the illustrated embodiment,the character buffer 22 and attribute buffer 24 can each contain asingle line of characters consisting of up to 36 characters. A dataoutput terminal of the display character buffer 22 is coupled to anaddress input terminal of a character ROM 30, and a data output terminalof the attribute buffer 24 is coupled to an address input terminal ofthe palette memory 40. In the illustrated embodiment, the palette memory40 is partitioned into separate foreground (42) and background (44)palettes. Specifically, a first data output terminal of the attributebuffer 24 is coupled to an address input terminal of the foregroundpalette 42 and a second data output terminal of the attribute buffer 24is coupled to an address input terminal of the background palette 44.One skilled in the art will understand that, although the RAM buffer 20,consisting of character buffer 22 and attribute buffer 24, and thepalette memory 40, consisting of foreground palette 42 and backgroundpalette 44 are illustrated as being separate elements, they may coexistwithin a single RAM in separately addressable partitions.

A color data output terminal of the foreground palette 42, producingthree component color values, is coupled to a first input terminal of amultiplexer 50, and an underline data output terminal of the foregroundpalette 42 is coupled to a corresponding input terminal of a selectlogic element 35. A color data output terminal of the background palette42, also producing three color component values, is coupled to a secondinput terminal of the multiplexer 50. A data output terminal of thecharacter ROM 30 is coupled to a second input terminal of the selectlogic element 35. An output terminal of the select logic element 35 iscoupled to a control input terminal of the multiplexer 50. A firstoutput terminal of the multiplexer 30, producing a first one of threecolor component signals, e.g. red (R), is coupled to a firstdigital-to-analog converter (DAC) 60R. Similarly, a second outputterminal of the multiplexer 30 is coupled to a green (G) color componentDAC 60G and a third output terminal of the multiplexer 30 is coupled toa blue (B) color component DAC 60B. Respective output terminals of thered, green and blue color component DACs, 60R, 60G and 60B, produceanalog signals representing color component signals of the currentlydisplayed character in the OSD image, and are coupled to correspondinginput terminals of a display device 70 which may include a televisionreceiver picture tube, for example.

The television receiver also includes a synchronization signal separator80. Other television receiver circuitry (not shown) may include an RF/IFtuner/amplifier front end circuitry coupled to an antenna or cabledistribution system; a video signal separator and video signalprocessing circuitry coupled to the front end circuitry; an audio signalseparator and audio signal processing circuitry also coupled to thefront end; and a scanning signal generator, coupled to thesynchronization separator 80. These elements operate in a known mannerto receive and demodulate an RF television signal, and to generate animage representative signal which is supplied to the display device 70,an audio signal which is supplied to speakers (not shown), anddeflection signals which are supplied to deflection coils on the displaydevice (also not shown) to control scanning of the display device, allin a known manner. An output terminal of the synchronization separator80 to an output terminal of a time base 90. Respective output terminalsof the time base 90 are coupled to corresponding address input terminalsof the RAM buffer 20 and the character ROM 30, and to an input terminalof the select logic element 35.

In operation, the synchronization signal separator 80 extracts andprocesses the synchronization component from the received compositetelevision signal, and supplies synchronization signals, such ashorizontal synchronization pulses, vertical synchronization pulses, anda clock signal synchronized to the color burst, to the time base 90. Thetime base unit 90 includes respective counters (not shown) synchronizedto the timing signals received from the synchronization signal separator80, and maintains those counters to identify the vertical line number,and horizontal line location, currently being scanned, all in a knownmanner.

The processor 10 stores data representing one line of an OSD image inthe RAM buffer 20. OSD display character representative data is storedin respective entries in the character buffer 22 and attributerepresentative data for those characters is stored in correspondingentries in the attribute buffer 24. The processor 10 can separatelyaddress and access each entry in the character buffer 22 and theattribute buffer 24. For example, the processor 10 may generate a menuwhich is to be displayed on the display device 70 soliciting input fromthe viewer via a remote control unit (not shown). Alternatively, closedcaptioning information may be extracted from the received televisionsignal in a known manner, and that information supplied to theprocessor, which, in turn, generates an OSD to display this informationon the display device 70. When this information is being stored in theRAM buffer 20 by the processor 10, only that information which isdifferent from the previous line is rewritten. For example, if theattributes for the characters in the new line of display characters arethe same as those in the previous line (the usual case), thoseattributes need not be rewritten.

TABLE I B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0

In a first illustrated embodiment, each display character entry in thecharacter buffer 22 is represented by an eight bit byte (see Table 1).Thus, up to 256 characters may be displayed. Each entry in the attributebuffer 24 is also an eight bit byte (see Table 1). The most significantfour bit nibble (FG3FG0) contains a pointer to one of sixteen entries inthe foreground palette 42, and the least significant four bit nibble(BG3BG0) contains a pointer to one of the sixteen entries in thebackground palette 45. The entries in both the foreground (42) and thebackground (44) palettes define a character's foreground and backgroundcolor, respectively, and also specify attributes such as underlining.

TABLE II B7 B6 B5 B4 B3 B2 B1 B0 FG3 FG2 FG1 FG0 BG3 BG2 BG1 BG0

TABLE III B7 B6 B5 B4 B3 B2 B1 B0 R1 R0 G1 G0 B1 B0

The process 10 also writes entries into the foreground palette 42 andthe background palette 44. As described above, up to sixteen foregroundand sixteen background palette entries are stored in the foregroundpalette 42 and background palette 44 respectively. In the firstillustrated embodiment, each entry in both the foreground and backgroundpalette consist of an eight bit byte. Each entry contains six bitsspecifying the color (foreground or background) of that entry, with twobits specifying each of the red (R1R0), green (G1G0) and blue (B1B0)color components for that color (see Table 3 for a background paletteentry). Each entry in the foreground palette also includes two bits forspecifying underlining (see Table 5 for a foreground palette entry).

FIG. 2 is a memory layout diagram of the image representative data for adisplay character within the character ROM 30 display character consistsof an array of pixels having 13 rows (row 012), each row having 9 pixels(pixel 08). Each pixel is either a foreground pixel or a backgroundpixel. This image is represented in the character ROM by a correspondingarray of ROM locations, each location containing data having one of twostates. For example, a foreground pixel may be represented by

TABLE IV B7 B6 B5 B4 B3 B2 B1 B0 U12 U11 R1 R0 G1 G0 B1 B0

logic ‘1’ data and a background pixel may be represented by logic ‘0’data. The data representing the image of the character itself iscontained within a subarray consisting of 9 rows (rows 19) of 8 pixels(pixel 18) substantially at the top right hand portion of the array. Theremainder of the array is blank (i.e. is specified to be the backgroundcolor) to provide space between characters, and between rows ofcharacters. The storage arrangement for a single character (thecharacter “A”) is illustrated in FIG. 2 by an array of squares, eachsquare representing one memory location in the character ROM 30. Aforeground pixel is represented by an “X” within a square, and abackground pixel is represented by a blank square.

Referring again to FIG. 1, respective portions of the vertical linecounter and horizontal location counter (not shown) in the time base 90address appropriate locations in the character buffer 22, the attributebuffer 24 and the character ROM 30 to extract the data specifying theOSD display character currently being displayed from the characterbuffer 22, its corresponding attributes from the attribute buffer 24,and the pixel of the specified OSD display character image currentlybeing scanned from the character ROM 30, respectively (described in moredetail below). In response to the foreground palette nibble at theoutput terminal of the attribute buffer 24 (see Table 5), one entry inthe foreground palette 42 is addressed. The foreground palette 42, inturn, produces the foreground color representative signal in theaddressed foreground palette entry, at its color data output terminal.The foreground palette also supplies the underlining data signal in theaddressed foreground palette entry to the select logic element 35.Similarly, in response to the background palette nibble at the outputterminal of the attribute buffer 24 (see Table 3), one entry in thebackground palette 44 is addressed. The background palette 44 producesthe background color representative signal in the addressed backgroundpalette entry, at its color data output terminal.

In response to the output byte from the character buffer 22, thelocation within the character ROM 30 where the array containing the datarepresenting the specified display character currently being scanned isstored (as illustrated in FIG. 2) is addressed. In response to portionsof the row and pixel counters from the time base 90, the row and pixelof that addressed array currently being scanned is then produced at thedata output terminal of the character ROM 30, in a known manner. Theoutput of the character ROM 30 is a signal representing the value of thepixel currently being displayed: either foreground or background. Thissignal is supplied to the select logic element 35. The select logicelement 35 monitors the row and pixel counters in the time base 90 todetermine which rows of the display character are currently beingscanned.

For the first 11 rows (row 010) of the character array (of FIG. 2) theoutput from the character ROM 30 is passed through the select logicelement 35 to the control input terminal of the multiplexer 50. If theoutput signal from the character ROM 30 specifies a foreground pixel,the multiplexer 50 is conditioned to couple the color data outputterminal from the foreground palette 42 to the color component DACs,60R, 60G and 60B. If the output signal from the character ROM 30specifies a background pixel, the multiplexer 50 is conditioned tocouple the color data output terminal from the background palette 42 tothe color component DACs, 60R, 60G and 60B. The analog signals producedby the DACs 60R, 60G and 60B are supplied to the display device 70,which displays the OSD image in response.

For the last two rows (rows 11 and 12) the underline data (U11 and U12,bits B6 and B7, respectively, of Table 5) from the foreground palette 42is used to control the multiplexer 50. If row 11 is being scanned, thenthe select logic element 35 examines the U11 bit (B6) from theforeground palette 42. If the U11 bit is a logic ‘1’ signal, then everypixel in row 11 is considered to be a foreground pixel. In this case,the select logic element 35 conditions the multiplexer 50 to coupled thecolor data output terminal from the foreground palette 42 to the colorcomponent DACs, 60R, 60G and 60B. If the U11 bit is a logic ‘0’ signal,then every pixel in row 11 is considered to be a background pixel. Inthis case, the select logic element 35 conditions the multiplexer 50 tocoupled the color data output terminal from the background palette 44 tothe color component DACs, 60R, 60G and 60B.

If row 12 is being scanned, then the select logic element 35 examinesthe U12 bit (B7) from the foreground palette 42. If the U12 bit is alogic ‘1’ signal, then every pixel in row 12 is considered to be aforeground pixel. In this case, the select logic element 35 conditionsthe multiplexer 50 to coupled the color data output terminal from theforeground palette 42 to the color component DACs, 60R, 60G and 60B. Ifthe U12 bit is a logic ‘0’ signal, then every pixel in row 12 isconsidered to be a background pixel. In this case, the select logicelement 35 conditions the multiplexer 50 to coupled the color dataoutput terminal from the background palette 44 to the color componentDACs, 60R, 60G and 60B. By setting the underline data (U11 and U12, bitsB6 and B7, respectively) in the foreground palette 42 appropriately, athick underline (consisting of both rows 11 and 12), or a thin underlinein one of two places (either row 11 or 12) may be specified.

An OSD system implemented in the manner described above allows for moresophisticated on-screen displays. Because twice as many displaycharacters may be specified in the character buffer 22, (i.e. 255characters, as compared to 127 for prior art versions), specializedscreen icons may be stored and displayed. In addition, any one ofsixteen foreground colors can be used with any one of sixteen backgroundcolors within a single character without inserting a space into thedisplay line. The sixteen foreground colors and sixteen backgroundcolors may be independently chosen from any of 64 possible colors. Also,the ability to independently control two lines for underlining allowsthicker drop shadows to be created. Flashing characters may be createdby periodically changing the color in the appropriate foreground paletteentry to the same color as the associated background palette entry.

TABLE V B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 U12 U11 S R2 R1 R0 G2 G1G0 B2 B1 B0

FIG. 3 is a block diagram of an alternate embodiment of an on-screendisplay system according to principles of the present invention. In FIG.3, elements which are the same as those in FIG. 1 are identified by thesame reference number and are not described in detail below. In FIG. 3,each entry in the foreground palette 42′ and background palette 44′ hasthree bits allocated to each of the three color components R, G and B.This makes a total of nine bits allocated in each palette entry todefine a color for 512 possible colors. The DACs 60′ operate as threebit DACs, instead of two bit DACs (60, of FIG. 1), as described above.In addition, the foreground palette 42′ includes two underline databits, and a solid color indicator bit S (B9), described in more detailbelow (see Table 5). Thus, each entry in the foreground palette 42′includes twelve bits. The background palette 44′ also includes a solidcolor indicator bit S (B9) (see Table 5). Thus, each entry in thebackground palette 44′ includes ten bits.

TABLE VI B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S R2 R1 R0 G2 G1 G0 B2 B1 B0

When an attribute byte is read from the attribute buffer 24, asdescribed above, a foreground color data signal, containing three colorcomponent signals, each having three bits, is coupled from theforeground palette 42′ to a first data input terminal of the multiplexer50′. Simultaneously, a background color data signal, containing threecolor component signals, each having three bits, is coupled from thebackground palette 44′ to a second data input terminal of themultiplexer 50′.

Also included in the embodiment illustrated in FIG. 3 is a fringepalette 100. The fringe palette contains a single ten bit entryidentical to the entries in the background palette 44′, as illustratedabove in Table 5. The output terminal of the processor 10 is alsocoupled to a data input terminal of the fringe palette 100, and theprocessor 10 may store a fringe color in the fringe palette 100 in asimilar manner to that for the foreground palette 42′ and the backgroundpalette 44′. The fringe palette 100 produces a fringe color data signal,containing three color component signals, each having three bits, at acolor data output terminal, which is coupled to a third input terminalof the multiplexer 50′.

In the OSD system illustrated in FIG. 3, the OSD image may have one ofthree colors: foreground and background colors, as described above; anda fringe color, e.g. for forming a border around the display area. Allareas of the OSD image which are not either foreground or backgroundareas are fringe areas. The select logic element 35′ is responsive tothe display character image data from the character ROM 30, and to rowand pixel location data from time base 90, as described above. Duringtimes when an OSD display character is to be displayed, the select logic35′ is responsive to data from the character ROM 30 to condition themultiplexer 50′ to couple the foreground color data signal from theforeground palette 42′ to the DACs 60′ when a foreground pixel is beingscanned, and to couple the background color data signal from thebackground palette 44′ to the DACs 60′ when a background pixel is beingscanned. During all other times when an OSD is to be generated (such asin a margin around the OSD image, or between display lines) the selectlogic element 35′ conditions the multiplexer 50′ to couple the colordata signal from the fringe palette 100 to the DACs 60′.

The solid data bit S (B9) from the foreground palette 42′ is coupled toa first input terminal of a second multiplexer 110, the solid data bit S(B9) from the background palette 44′ is coupled to a second inputterminal of the second multiplexer 110, and the solid data bit S (B9)from the fringe palette 100 is coupled to a third input terminal of thesecond multiplexer 110. The second multiplexer 110 is conditioned by thesame control signal from the select logic element 35′ as the firstmentioned multiplexer 50′. Thus, when a foreground pixel is beingdisplayed, the solid data bit S from the foreground palette 42′ isproduced at the output terminal of the second multiplexer 110, when abackground pixel is being displayed, the solid data bit S from thebackground palette 44′ is produced, and when a fringe pixel is beingdisplayed, the solid data bit S from the fringe palette 100 is produced.

The solid data bit S produced at the output terminal of the secondmultiplexer 110 is coupled to a control input terminal of the displaydevice 70′. This data bit controls the blanking of the television imagesignal from the received television signal (not shown). When this bit isa logic ‘1’ signal, then the television image signal is blanked whilethis pixel is being displayed. This causes the OSD color being displayed(foreground, background or fringe) to appear to be a solid color. Whenthis bit is a logic ‘0’ signal, then the television image signal is notblanked, and is combined with the OSD image signal. In this case, theOSD color being displayed appears to be transparent, allowing theunderling television image to show through. The output of the secondmultiplexer 110 is coupled to the blanking circuitry (not shown, butpresent in the display device 70), and conditions it to operate asdescribed above.

An OSD system illustrated in FIG. 3 provides for up to sixteenindependently selectable foreground and background colors selected from512 possible colors, and one fringe color, also selected from 512possible colors. In addition, each palette entry in the foregroundpalette 42′, the background palette 44′ and the fringe palette 100 maybe specified to appear as a solid color or a transparent overlay atopthe received television image. This permits extra flexibility over theOSD system illustrated in FIG. 1 with very little extra circuitry.

FIG. 4 is a block diagram of another alternate embodiment of anon-screen display system according to principles of the presentinvention. In FIG. 4, elements which are the same as those in FIGS. 1and 3 are identified by the same reference number and are not describedin detail below. In FIG. 4, a portion of the attributes for each displaycharacter represented by an entry in the character buffer 22 iscontained in the corresponding entry in the attribute buffer 24″ (seeTable 6). Each attribute entry is represented by an eight bit byte, withone four bit nibble, P0P3 (B0B3), specifying one of sixteen paletteentries, in a similar manner to that described above. The four bitnibble specifying the palette entry for the corresponding displaycharacter is coupled to an address input terminal of a palette memory40″.

However, the remaining four bit nibble specifies some attributes for thecorresponding display character entry in the character buffer 22. Onebit, F (B7 of Table 6), controls whether the corresponding displaycharacter is flashing; one bit, I (B6) controls whether thecorresponding display character is displayed in italic (slanted); andtwo bits, U12 and U11 (B4B5), control the underlining for thecorresponding display character in a manner similar to that describedabove. The four bit nibble specifying

TABLE VII B7 B6 B5 B4 B3 B2 B1 B0 F I U12 U11 P3 P2 P1 P0

attributes of the corresponding display character is coupled to acontrol input terminal of the select logic element 35″.

The select logic element 35″ responds to the underline data signal, U11and U12, in the same manner described above to generate an underline forthe display character specified in the corresponding entry in thecharacter buffer 22. When the flash attribute signal, F (B7 of Table 6),is a logic ‘1’ signal, the select logic element 35″ operates torepeatedly first force all the pixels in the array containing thedisplay character image to be background pixels (by conditioning thefirst multiplexer 50′ to couple the background color signal outputterminal from the palette 40″ to the DACs 60′) for a first period oftime; and then restore the normal operation described above for a secondperiod of time, all in a known manner. This creates an OSD displaycharacter which appears to flash on the screen. When the flash attributesignal, F, is a logic ‘0’ signal, the character is displayed in thenormal manner described above, and no flashing occurs.

When the italic attribute signal, I (B6 of Table 6), the select logicelement 35″ changes the display times of the respective rows of pixelsin the array of pixels in a manner to produce an image of a characterwhich appears to be slanted, also in a known manner. When the italicattribute signal, I, is a logic ‘0’ signal, the character is displayedin the normal manner described above, and appears upright.

In the embodiment illustrated in FIG. 4, only a single palette 40″,containing sixteen entries, is provided. Each entry in the palette 40″contains both foreground and background color data (see Table 8). Eachcolor component in both the foreground and background color isrepresented by two bits, although three (or more) could also be used.Thus, six bits are allocated for the foreground color (red component:FR1&FR0 (B12B13 ), green component: FG1&FG0 (B10B11), and blue componentFB1&FB0 (B8B9)) and the background color (red component: BR1&BR0 (B4B5),green component: BG1BG0 (B2B3), and blue component: BB1BB0 (B0B1))within each palette entry. Each palette entry also includes a solidcolor data bit for the foreground FS (B14) and

TABLE VIII B15 B14 B13 B12 B11 B10 B9 B8 FS FR1 FR0 FG1 FG0 FB1 FB0 B7B6 B5 B4 B3 B2 B1 B0 BS BR1 BR0 BG1 BG0 BB1 BB0

background BS (B6). In FIG. 4, each palette entry consists of two bytes,with foreground data in one byte and background data in the other. Thefringe palette 100 contains a single one byte entry corresponding to theportion of the palette 40″ entry containing the background data, whichcontains a color data signal C and a solid color bit S.

When the time base 90 addresses a display character entry in thecharacter buffer 22 and a corresponding attribute entry in the attributebuffer 24″, the nibble specifying the entry in the palette 40″conditions the palette to simultaneously produce: the background colordata signal at the background color data output terminal BG C; thebackground solid data bit at the background solid data output terminalBG S; the foreground color data signal at the foreground color dataoutput terminal FG C; and the foreground solid data bit at theforeground solid data output terminal FG S. The color data signals fromthe palette 40″ foreground color signal output terminal, FG C, thepalette 40″ background color signal output terminal, BG C, and thefringe palette 100 color signal output terminal C are coupled torespective input terminals of the first multiplexer 50′. Similarly, thesolid color data bits from the palette 40″ foreground solid color bitoutput terminal, FG S, the palette 40″ background solid color bit outputterminal, BG S, and the fringe palette 100 solid color bit outputterminal S are coupled to respective input terminals of the secondmultiplexer 110.

The first multiplexer 50′ operates as described above with respect toFIG. 3 to supply the appropriate one of the foreground, background andfringe color signal to the DACs 60′, which, in turn, supply the analogcolor signals to the display device 70 to generate the OSD image.Similarly, the second multiplexer 110 operates as described above tosupply the appropriate one of the foreground, background and fringesolid color bit signal to the display device 70 to control the blankingof the received television image signal.

One skilled in the art will understand that other attributes for thedisplayed OSC characters and fringe areas may be controlled by theaddition of extra bits to the foreground, background and/or fringepalettes; and/or the attribute buffer, those bits controllingappropriate circuitry in the OSD system or display device 70′ togenerate those attributes. For example, a bit may be included in thebackground palette specifying whether the background color begins at theleft edge of the pixel array defining the display character, or beginsin the middle of that array. One skilled in the art will also understandthat other allocations of attribute control bits among the attributebuffer, and the foreground and background palettes may also be made.

What is claimed is:
 1. An on-screen display system, comprising: acharacter buffer containing a plurality of entries, each entryspecifying one of a predetermined plurality of display characters; anattribute buffer containing a plurality of entries respectivelycorresponding to the plurality of entries in the display characterbuffer, each entry specifying an attribute of the corresponding displaycharacter; and control circuitry for substantially simultaneouslyretrieving corresponding entries from the character and attributebuffers and generating a signal representing the image of the displaycharacter specified in the retrieved display character entry having theattribute specified in the retrieved attribute entry; wherein each entryin the attribute contains data specifying one of a plurality of entriesin a palette memory; and said control circuitry comprises: a characterread-only memory, coupled to the character buffer, and containing aplurality of arrays of pixels, each pixel being one of a foregroundpixel or a background pixel, respectively corresponding to thepredetermined plurality of display characters, for producing a signalrepresenting a pixel in the pixel array corresponding to the displaycharacter specified by the retrieved display character entry; saidpalette memory is coupled to the attribute buffer and contains aplurality of entries specifying respective image characteristics forforeground pixels and background pixels for producing respective signalsrepresenting the image characteristics of foreground and backgroundpixels in the palette entry specified by the retrieved attribute entry,said palette memory also containing an attribute control signal;selector means for receiving said pixel representative signal andattribute control signal; and a multiplexer, having first and seconddata input terminals responsive to the foreground and background pixelimage representative signals from the palette memory, and having acontrol input connected to said selector for receiving either the pixelrepresentative signal for producing the OSD image representative signal.2. The OSD system of claim 1, wherein: the palette memory (40) ispartitioned into a foreground palette (42) containing a first pluralityof entries, each entry specifying image characteristics for foregroundpixels, and a background palette (42) containing a second plurality ofentries, each entry specifying image characteristics for backgroundpixels; and the palette entry specifying data in the attribute buffer(24) contains a first portion specifying one of the first plurality offoreground palette entries, and a second portion specifying one of thesecond plurality of background palette entries.
 3. The OSD system ofclaim 1 wherein: each entry in the palette memory (40) includes datarepresenting the color of foreground pixels and background pixels; andthe control circuitry comprises circuitry (60R,60G,60B), coupled to theoutput of the multiplexer (50), for generating color representativesignals (R,G,B) corresponding to the specified entry in the palettememory (40).
 4. The OSD system of claim 3, wherein: the attributecontrol signal controls the image of the display character specified bythe retrieved character buffer entry to be underlined.
 5. The OSD systemof claim 3, wherein: the attribute control signal controls the image ofthe display character specified by the retrieved character buffer entryto flash.
 6. The OSD system of claim 3, wherein: the attribute controlsignal controls the image of the display character specified by theretrieved character buffer entry to be italic.
 7. The OSD system ofclaim 1, wherein: a processor (10), coupled to the character buffer(22), the attribute buffer (24) and the palette memory (40) for storingdisplay character specification data in respective entries of thecharacter buffer (22), attribute specification data in respectiveentries in the attribute buffer (24) and foreground and background pixelimage characteristic data in the palette memory (40).
 8. The OSD systemof claim 1, wherein: the control circuitry comprises circuitry forcombining an image representing a television signal and the displaycharacter image representative signal, including circuitry (110,70) forselectively blanking the television image representative signal inresponse to a control signal; and the palette memory (40) storesforeground and background pixel image characteristic data in each entryincluding data for generating the control signal for the selectiveblanking circuitry.
 9. The OSD system of claim 1, wherein: a processor(10), coupled to the buffer (22) and the attribute buffer (24), forstoring display character specification in respective entries of thecharacter buffer (22) and attribute specification data in respectiveentries in the attribute buffer (24).
 10. The OSD system of claim 1,wherein: timing circuitry (80,90) responsive to a television signal, andcoupled to the character buffer (22), the attribute buffer (24) and thecontrol circuitry, for synchronizing the display character imagerepresentative signal to the television signal.
 11. The OSD system ofclaim 10 wherein the control circuitry comprises circuitry (70′) forcombining an image represented by the television signal and the displaycharacter image representative signal.